000 00446nam a2200193Ia 4500
008 221105s9999 xx 000 0 und d
020 _a9788131706336
041 _aENGLISH
082 _a621.395 YAL
082 _bSUD
100 _aSUDHAKAR YALAMANCHILI.
245 0 _aINTRODUCTORY VHDL FROM SIMULATION TO SYNTHESIS
250 _a-
260 _bPEARSON.
260 _c2013
300 _a401 p.
650 _aVLSI DESIGN
942 _cBK
999 _c36137
_d36137