JOHN P UYEMURA. <br/><br/>
CHIP DESIGN FOR SUBMICRON VLSI : CMOS LAYOUT AND SIMULATION 

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 -  CENGAGE LEARNING.  2013 
 - 411 p. 
<br/><br/><label>ISBN: </label>9788131501955 
<br/><br/><label>Subjects--Topical Terms: </label><br/>VLSI DESIGN
<br/><br/><label>Dewey Class. No.: </label>621.395 UYE  / JOH