CHIP DESIGN FOR SUBMICRON VLSI : CMOS LAYOUT AND SIMULATION
JOHN P UYEMURA
CHIP DESIGN FOR SUBMICRON VLSI : CMOS LAYOUT AND SIMULATION - - THOMSON LEARNING 2006 - 411
8131501957
VLSI DESIGN
621.395 / JOH
CHIP DESIGN FOR SUBMICRON VLSI : CMOS LAYOUT AND SIMULATION - - THOMSON LEARNING 2006 - 411
8131501957
VLSI DESIGN
621.395 / JOH